-
I was sniffing round the source code, and was excited to see that "enabled_when_ready" was an option, but cannot seem to get it to accept it in my bs classic code? Does it actually exist, or maybe just in bsv? |
Beta Was this translation helpful? Give feedback.
Replies: 1 comment 2 replies
-
The feature is not documented and not really tested, so in that respect it doesn't exist. The BSV parser does accept it and BSC does do something when it sees that attribute, but it's probably not the right behavior or the full behavior. So some work would be needed. The one file in the test suite that has this attribute is I believe that BSC would need to be fixed up to (1) not generate the unused EN port, (2) extend the information that is recorded about synthesized modules (what you can specify in import-BVI and what BSC internally generates for synthesized modules) to support "enabled_when_ready" as a property of action methods, and (3) have BSC check this property on submodules. And I guess also: (4) support the pragma in BH, (5) add tests to the suite, and (6) add it to the BH and BSV reference guides. For reference, you could see how The check is performed after elaboration and scheduling, in the stage The removal of the port happens later. For Verilog, that is possibly in So that might be a key to how to represent this attribute in the scheduling information. Right now, the way that always-enabled is recorded is by indicating that the EN port is Anyway, adding support in BH should be trivial. And fixing up the rest of the behavior should also be easy. |
Beta Was this translation helpful? Give feedback.
The feature is not documented and not really tested, so in that respect it doesn't exist.
The BSV parser does accept it and BSC does do something when it sees that attribute, but it's probably not the right behavior or the full behavior. So some work would be needed.
The one file in the test suite that has this attribute is
bsc.bluesim/to_systemc/getput/GetPutTest.bsv
, so you can compile that and see what the behavior is. I believe that what BSC does is, when generating a module that has anenabled_when_ready
attribute, to generate Verilog that uses the RDY signal anywhere it would normally use the EN signal, and to still generate the EN port, but it is unused; there is no check that subm…