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I'm building my own register file with some custom functionality in Verilog. The built-in regfile has 5 read ports (explicitly described in the RTL design) which are exposed through a single method, Based on the documentation I can find, I can only assign a single set of I/O ports to a given BSV method name when using the How can I expose multiple read ports through a single BSV method with my design (similar to the built-in RF)? |
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This feature is called "multiplicity". It has been in BSC since the very beginning, but is probably only ever used for the The multiplicity can be specified with brackets in the BH/Classic import statement. For example, here is a line from an import in
My sense was that the BSV syntax (import-BVI) did not support multiplicity. And the BSV Reference Guide does not mention it in the syntax. However... I do see this line in the BSV parser code:
This parses a multiplicity number in brackets following the name of the method. So I tried an example:
And this worked! So, apparently, the answer to your question is that you can include a number after the method name, such as |
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This feature is called "multiplicity". It has been in BSC since the very beginning, but is probably only ever used for the
RegFile
primitives. It's quite possible that a better feature / methodology could be thought up now. (For example, folks at MIT explored features such as "Performance Guarantees" that would cause the compiler to duplicate ports as necessary, although that was for user-written code, where the method definition could be duplicated.)The multiplicity can be specified with brackets in the BH/Classic import statement. For example, here is a line from an import in
RegFile.bs
, where the multiplicity of 5 is specified:My sense was that the B…