From 51a96a2cba2fd2882b6fa13405105160fa91a47c Mon Sep 17 00:00:00 2001 From: Asahi Lina Date: Thu, 15 Jun 2023 01:34:45 +0900 Subject: [PATCH] drm/asahi: render: Fix meta1_blocks calculation for MSAA Block count needs to be computed with an extra factor of the sample count. Signed-off-by: Asahi Lina --- drivers/gpu/drm/asahi/hw/t600x.rs | 2 +- drivers/gpu/drm/asahi/queue/render.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/asahi/hw/t600x.rs b/drivers/gpu/drm/asahi/hw/t600x.rs index 842f4cd1820a8b..d54f1d4a61f95c 100644 --- a/drivers/gpu/drm/asahi/hw/t600x.rs +++ b/drivers/gpu/drm/asahi/hw/t600x.rs @@ -62,7 +62,7 @@ pub(crate) const HWCONFIG_T6002: super::HwConfig = HwConfig { preempt3_size: 0x20, clustering: Some(HwClusteringConfig { meta1_blocksize: 0x44, - meta2_size: 0x190 * 8, // CHECK + meta2_size: 0xc0 * 8, meta3_size: 0x280 * 8, meta4_size: 0x30 * 16, max_splits: 16, diff --git a/drivers/gpu/drm/asahi/queue/render.rs b/drivers/gpu/drm/asahi/queue/render.rs index 292a3b2f06d125..1b0e24e53c3882 100644 --- a/drivers/gpu/drm/asahi/queue/render.rs +++ b/drivers/gpu/drm/asahi/queue/render.rs @@ -136,7 +136,7 @@ impl super::Queue::ver { // No idea where this comes from, but it fits what macOS does... // TODO: layers? let meta1_blocks = if num_clusters > 1 { - div_ceil(align(tiles_x, 2) * align(tiles_y, 4), 0x1980) + div_ceil(align(tiles_x, 2) * align(tiles_y, 4) * cmdbuf.samples, 0x1980) } else { 0 };