New rule: one interface definition per file

[prajapati93]

New rule check: One interface definition per file.

Benefits of having only one interface definition per SystemVerilog file:

• Readability and Maintainability: Multiple interface definitions in a single file can make code hard to read and edit, leading to errors and confusion.
• Namespace Management: SystemVerilog's hierarchical namespace can become unwieldy when dealing with multiple interfaces in one file, potentially causing conflicts.
• Tool Compatibility: Some SystemVerilog tools, like linters and debuggers, may not work well with files containing multiple interfaces.
• Reuse Challenges: Reusing interfaces from a file with multiple interfaces can lead to code duplication and hinder codebase maintenance.

Specific problems with multiple interfaces in one file:

• Ambiguity: Identical interface names within the same file can confuse the compiler.
• Circular Dependencies: Interdependent interfaces in the same file may cause compiler failures.
• Hidden Side Effects: Shared signals in the same file can make it challenging to track changes.

To maintain clean, readable, and error-free code, it's recommended to have one interface per SystemVerilog file. Organize your code by creating separate files for each interface, using matching filenames, grouping related interfaces in directories, and using packages to structure your code effectively. This approach enhances code organization and maintainability.

Expected output when there are more than one interface declared in a file:
PySlint: Violation: [REUSE_ONE_INTF_PER_FILE]: Always use one-interface definition per file