From acbe271021b38ee9cf7fbcc6129ad157573fec60 Mon Sep 17 00:00:00 2001 From: nipulkumar-11 <79196196+nipulkumar-11@users.noreply.github.com> Date: Thu, 22 Sep 2022 18:00:49 +0530 Subject: [PATCH 01/13] OVL_EVEN_PARITY support files for checker OVL_EVEN_PARITY --- .../ivl_uvm_ovl_alw/Makefile | 23 +++--- .../ivl_uvm_ovl_alw/OVL_EVEN_PARITY | 19 +++++ .../ivl_uvm_ovl_even_parity_fail.sv | 78 +++++++++++++++++++ .../ivl_uvm_ovl_even_parity_pass.sv | 63 +++++++++++++++ 4 files changed, 169 insertions(+), 14 deletions(-) create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_EVEN_PARITY create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_even_parity_fail.sv create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_even_parity_pass.sv diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/Makefile b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/Makefile index 80c88f9..327771f 100644 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/Makefile +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/Makefile @@ -1,17 +1,12 @@ -all: clean pass fail - -pass: - iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_a_alw_pass.sv >& pass_comp.log - #iverilog -s test -I../../ivl_uvm_std_ovl/ ../../ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v ivl_uvm_ovl_ex.sv |& tee comp.log - vvp a.out >& pass_run.log - -fail: - iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_a_alw_fail.sv >& fail_comp.log - vvp a.out >& fail_run.log - +all: + make --no-print-directory -f OVL_EVEN_PARITY + make --no-print-directory -f OVL_WIN_CHANGE + make --no-print-directory -f OVL_FIFO_INDEX clean: - rm -fr a.out *.log *.vcd tee - - + rm -fr a.out *.log *.vcd tee +help: + make --no-print-directory -f OVL_EVEN_PARITY help + make --no-print-directory -f OVL_WIN_CHANGE help + make --no-print-directory -f OVL_FIFO_INDEX help \ No newline at end of file diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_EVEN_PARITY b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_EVEN_PARITY new file mode 100644 index 0000000..59b7f18 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_EVEN_PARITY @@ -0,0 +1,19 @@ +all: clean ovl_even_parity_pass ovl_even_parity_fail help + + +ovl_even_parity_pass: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_even_parity_pass.sv>& pass_comp.log + vvp a.out >& pass_run.log + +ovl_even_parity_fail: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_even_parity_fail.sv >& fail_comp.log + vvp a.out >& fail_run.log + +clean: + rm -fr a.out *.log *.vcd tee + +help: + @echo "(Targets - clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_change_pass ovl_win_change_fail )" + + + diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_even_parity_fail.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_even_parity_fail.sv new file mode 100644 index 0000000..932b298 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_even_parity_fail.sv @@ -0,0 +1,78 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, wn, rn; + reg DATAIN; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_even_parity + ovl_even_parity u_ovl_even_parity ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .test_expr (DATAIN) + + ); + + + + +initial begin + reset = 0; wn = 0; rn = 0; + wait_clks(5); + + reset = 1; + wait_clks(5); + + + $display("Start testing"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 1"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 2"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 3"); + + + $display("real parity injecting 1"); + DATAIN = 1; + wait_clks(1); + + + $display("real parity injecting 2"); + DATAIN = 2; + wait_clks(1); + + $display("Real parity injecting 3"); + DATAIN = 99; + wait_clks(1); + + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_even_parity_pass.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_even_parity_pass.sv new file mode 100644 index 0000000..6203812 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_even_parity_pass.sv @@ -0,0 +1,63 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, wn, rn; + reg DATAIN; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_even_parity + ovl_even_parity u_ovl_even_parity ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .test_expr (DATAIN) + + ); + + + + +initial begin + reset = 0; wn = 0; rn = 0; + wait_clks(5); + + + + $display("Start testing"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 1"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 2"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 3"); + + + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule From 38f7ffd2f327b4efe2fa31193717b3a16ab74fa6 Mon Sep 17 00:00:00 2001 From: nipulkumar-11 <79196196+nipulkumar-11@users.noreply.github.com> Date: Thu, 22 Sep 2022 18:03:11 +0530 Subject: [PATCH 02/13] OVL_FIFO_INDEX support files for OVL_FIFO_INDEX --- .../ivl_uvm_ovl_alw/OVL_FIFO_INDEX | 18 ++++ .../ivl_uvm_ovl_fifo_index_fail.sv | 96 +++++++++++++++++++ .../ivl_uvm_ovl_fifo_index_pass.sv | 54 +++++++++++ 3 files changed, 168 insertions(+) create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_FIFO_INDEX create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_fifo_index_fail.sv create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_fifo_index_pass.sv diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_FIFO_INDEX b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_FIFO_INDEX new file mode 100644 index 0000000..4f9f83e --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_FIFO_INDEX @@ -0,0 +1,18 @@ +all: clean ovl_fifo_index_pass ovl_fifo_index_fail help + +ovl_fifo_index_pass: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_fifo_index_pass.sv>& pass_comp.log + vvp a.out >& pass_run.log + +ovl_fifo_index_fail: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_fifo_index_fail.sv >& fail_comp.log + vvp a.out >& fail_run.log + +clean: + rm -fr a.out *.log *.vcd tee + +help: + @echo "(Targets - clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_change_pass ovl_win_change_fail )" + + + diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_fifo_index_fail.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_fifo_index_fail.sv new file mode 100644 index 0000000..4616364 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_fifo_index_fail.sv @@ -0,0 +1,96 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, wn, rn; + reg [7:0] DATAIN; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_fifo_index + ovl_fifo_index u_ovl_fifo_index ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .push (wn), + .pop (rn) + ); + + // Instantiate OVL example - ovl_even_parity +// ovl_even_parity u_ovl_even_parity ( +// .clock (clk), +// .reset (reset), +// .enable (1'b1), +// .test_expr (DATAOUT[0]) +// +// ); + + + + +initial begin + reset = 0; wn = 0; rn = 0; + wait_clks(5); + + reset = 1; + wait_clks(5); + + + $display("Start testing"); + $display("Underflow injecting"); + wn = 0; rn = 1; + wait_clks(5); + + wn = 1; rn = 0; + wait_clks(5); + + $display("overflow injecting"); + wn = 1; rn = 0; + wait_clks(5); + + wn = 1; rn = 0; + wait_clks(5); + + wn = 1; rn = 0; + wait_clks(5); + + + wn = 1; rn = 0; + wait_clks(5); + + + wn = 1; rn = 0; + wait_clks(5); + + + wn = 1; rn = 0; + wait_clks(5); + + + wn = 1; rn = 0; + wait_clks(5); + + + wn = 1; rn = 0; + wait_clks(5); + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_fifo_index_pass.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_fifo_index_pass.sv new file mode 100644 index 0000000..5d0ea85 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_fifo_index_pass.sv @@ -0,0 +1,54 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, wn, rn; + reg [7:0] DATAIN; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_fifo_index + ovl_fifo_index u_ovl_fifo_index ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .push (wn), + .pop (rn) + ); + +initial begin + reset = 0; wn = 0; rn = 0; + wait_clks(5); + + reset = 1; + wait_clks(5); + + $display("Start testing"); + + $display(" Writing"); + + wn = 1; rn = 0; + wait_clks(1); + + + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule From e43664db44a72ccb08216176c5742c1ed81cd323 Mon Sep 17 00:00:00 2001 From: nipulkumar-11 <79196196+nipulkumar-11@users.noreply.github.com> Date: Thu, 22 Sep 2022 18:06:17 +0530 Subject: [PATCH 03/13] OVL_WIN_CHANGE suppor file for OVL_WIN_CHANGE --- .../ivl_uvm_ovl_alw/OVL_WIN_CHANGE | 18 ++++ .../ivl_uvm_ovl_win_change_fail.sv | 96 +++++++++++++++++++ .../ivl_uvm_ovl_win_change_pass.sv | 85 ++++++++++++++++ 3 files changed, 199 insertions(+) create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_WIN_CHANGE create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_win_change_fail.sv create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_win_change_pass.sv diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_WIN_CHANGE b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_WIN_CHANGE new file mode 100644 index 0000000..5f5d2bd --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_WIN_CHANGE @@ -0,0 +1,18 @@ +all: clean ovl_win_change_pass ovl_win_change_fail help + +ovl_win_change_pass: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_win_change_pass.sv>& pass_comp.log + vvp a.out >& pass_run.log + +ovl_win_change_fail: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_win_change_fail.sv>& fail_comp.log + vvp a.out >& fail_run.log + +clean: + rm -fr a.out *.log *.vcd tee + +help: + @echo "(Targets - clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_change_pass ovl_win_change_fail )" + + + diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_win_change_fail.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_win_change_fail.sv new file mode 100644 index 0000000..a615a76 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_win_change_fail.sv @@ -0,0 +1,96 @@ +// This is linear queue / FIFO +// The queue length 1 +// CASES A ,C ,and D should expect as fail + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, rd,rd_ack,DATA; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_even_parity + ovl_win_change u_ovl_win_change ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .start_event(rd), + .test_expr (DATA), + .end_event(rd_ack) + + ); + + + + +initial begin + reset = 0; rd = 0; rd_ack = 0; + wait_clks(5); + + reset =1; + wait_clks(5); + + + + $display("Start testing"); + + $display("1 A with no change in data"); + + DATA = 0; rd =1; rd_ack =0; + wait_clks(1); + $display("A"); + + + DATA = 0; rd_ack =1; + wait_clks(1); + $display("2 A with no change in data"); + + + $display("1 B with change in data"); + DATA = 1; rd =1;rd_ack =0; + wait_clks(1); + $display("B"); + + DATA = 0; rd_ack =1; + wait_clks(1); + $display("2 B with change in data"); + + $display("1 C with no change in data"); + DATA = 1; rd =1;rd_ack =0; + wait_clks(1); + $display("C"); + + DATA = 1; rd_ack =1; + wait_clks(1); + $display("2 C with no change in data"); + + + $display("1 D with no change in data"); + DATA = 1; rd =1;rd_ack =0; + wait_clks(1); + $display("D"); + + DATA = 1; rd_ack =1; + wait_clks(1); + $display("2 D with no change in data"); + + + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_win_change_pass.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_win_change_pass.sv new file mode 100644 index 0000000..4d8a783 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_win_change_pass.sv @@ -0,0 +1,85 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, rd,rd_ack,DATA; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_even_parity + ovl_win_change u_ovl_win_change ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .start_event(rd), + .test_expr (DATA), + .end_event(rd_ack) + + ); + + + + +initial begin + reset = 0; rd = 0; rd_ack = 0; + wait_clks(5); + + reset =1; + wait_clks(5); + + + + $display("Start testing"); + + $display("1 A with change in data"); + + DATA = 1; rd =1; rd_ack =0; + wait_clks(1); + $display("A"); + + + DATA = 0; rd_ack =1; + wait_clks(1); + $display("2 A with change in data"); + + + $display("1 B with change in data"); + DATA = 1; rd =1;rd_ack =0; + wait_clks(1); + $display("B"); + + DATA = 0; rd_ack =1; + wait_clks(1); + $display("2 B with change in data"); + + $display("1 D with change in data"); + DATA = 1; rd =1;rd_ack =0; + wait_clks(1); + $display("D"); + + DATA = 0; rd_ack =1; + wait_clks(1); + $display("2 D with change in data"); + + + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule From e1d912e0607784aa5dd7a06d507c46fefd0f5f1d Mon Sep 17 00:00:00 2001 From: nipulkumar-11 <79196196+nipulkumar-11@users.noreply.github.com> Date: Thu, 22 Sep 2022 18:19:32 +0530 Subject: [PATCH 04/13] README info - how to run the checker --- ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README new file mode 100644 index 0000000..a128223 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README @@ -0,0 +1,10 @@ +main makefile - Makefile + +Main will invoke each checker makefile as below names +OVL_EVEN_PARITY +OVL_WIN_CHANGE +OVL_FIFO_INDEX + + +make all [this will run all chekcer makefiles wih pass and fail cases] +make help [this will show which are the targets for indiviadual checker] From 16ebefdda20fd40cf73f8f484c3cb83f7242b60b Mon Sep 17 00:00:00 2001 From: nipulkumar-11 <79196196+nipulkumar-11@users.noreply.github.com> Date: Thu, 22 Sep 2022 18:20:34 +0530 Subject: [PATCH 05/13] Update README --- ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README index a128223..46a5d41 100644 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README @@ -6,5 +6,5 @@ OVL_WIN_CHANGE OVL_FIFO_INDEX -make all [this will run all chekcer makefiles wih pass and fail cases] +make all [this will run each chekcer makefiles (wih pass and fail cases) ] make help [this will show which are the targets for indiviadual checker] From 671bb39732512ecb992ff02c0c5e94272254592e Mon Sep 17 00:00:00 2001 From: nipulkumar-11 <79196196+nipulkumar-11@users.noreply.github.com> Date: Thu, 22 Sep 2022 18:30:15 +0530 Subject: [PATCH 06/13] steps added Info - 1. Makefile flow 2. To Run individual checker --- .../ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README index 46a5d41..11fc34d 100644 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README @@ -1,3 +1,4 @@ +---------------->>>>>>>>>>>>>>>> Makefile flow main makefile - Makefile Main will invoke each checker makefile as below names @@ -6,5 +7,33 @@ OVL_WIN_CHANGE OVL_FIFO_INDEX +---------------->>>>>>>>>>>>>>>> To Run all checker + make all [this will run each chekcer makefiles (wih pass and fail cases) ] make help [this will show which are the targets for indiviadual checker] + +---------------->>>>>>>>>>>>>>>> To Run individual checker + +[1] ovl_fifo_index_pass +% make -f OVL_FIFO_INDEX ovl_fifo_index_pass +iverilog -g2012 -s test -I/c/ivl_uvm-main1/ivl_uvm-main/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_fifo_index_pass.sv>& pass_comp.log +vvp a.out >& pass_run.log + + + +% cat pass_run.log +OVL_NOTE: V2.8: OVL_FIFO_INDEX initialized @ test.u_ovl_fifo_index.ovl_init_msg_t Severity: 1, Message: VIOLATION +test.u_clk_100 FREQ_IN_MHZ = 100.000 MHz +test.u_clk_100 PERIOD = 10.000 ns +VCD info: dumpfile dump.vcd opened for output. +Start testing + Writing +ivl_uvm_ovl_fifo_index_pass.sv:44: $finish called at 110000000 (1fs) + + + + +[2] ovl_fifo_index_fail +% make -f OVL_FIFO_INDEX ovl_fifo_index_fail +iverilog -g2012 -s test -I/c/ivl_uvm-main1/ivl_uvm-main/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_fifo_index_fail.sv >& fail_comp.log +vvp a.out >& fail_run.log From f71b23bb6c2c42ca2be27f6d4e7a44ee3378e39c Mon Sep 17 00:00:00 2001 From: nipulkumar-11 <79196196+nipulkumar-11@users.noreply.github.com> Date: Thu, 22 Sep 2022 18:31:05 +0530 Subject: [PATCH 07/13] Update README --- ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README index 11fc34d..9fd31f6 100644 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README @@ -9,7 +9,7 @@ OVL_FIFO_INDEX ---------------->>>>>>>>>>>>>>>> To Run all checker -make all [this will run each chekcer makefiles (wih pass and fail cases) ] +make all [this will run each chekcer makefiles (with pass and fail cases) ] make help [this will show which are the targets for indiviadual checker] ---------------->>>>>>>>>>>>>>>> To Run individual checker From 17c4c99d686b23006066080ca2661c28a1401c42 Mon Sep 17 00:00:00 2001 From: nipulkumar-11 <79196196+nipulkumar-11@users.noreply.github.com> Date: Thu, 22 Sep 2022 18:35:39 +0530 Subject: [PATCH 08/13] waveform in GTK wave To see the waveform in GTK wave --- .../ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README index 9fd31f6..31f1f40 100644 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README @@ -19,8 +19,6 @@ make help [this will show which are the targets for indiviadual checker] iverilog -g2012 -s test -I/c/ivl_uvm-main1/ivl_uvm-main/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_fifo_index_pass.sv>& pass_comp.log vvp a.out >& pass_run.log - - % cat pass_run.log OVL_NOTE: V2.8: OVL_FIFO_INDEX initialized @ test.u_ovl_fifo_index.ovl_init_msg_t Severity: 1, Message: VIOLATION test.u_clk_100 FREQ_IN_MHZ = 100.000 MHz @@ -30,10 +28,17 @@ Start testing Writing ivl_uvm_ovl_fifo_index_pass.sv:44: $finish called at 110000000 (1fs) - - - [2] ovl_fifo_index_fail % make -f OVL_FIFO_INDEX ovl_fifo_index_fail iverilog -g2012 -s test -I/c/ivl_uvm-main1/ivl_uvm-main/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_fifo_index_fail.sv >& fail_comp.log vvp a.out >& fail_run.log + +---------------->>>>>>>>>>>>>>>> To see the waveform in GTK wave + +pacman -S mingw-w64-x86_64-gtkwave --> to install GTK wave + +then after running the test with make it will create a dump.vcd + +gtkwave -o -t des.stems dump.vcd des.sav + + From a9dce11db0eb48e6325ab67070da6e9e0edc628d Mon Sep 17 00:00:00 2001 From: nipulkumar-11 <79196196+nipulkumar-11@users.noreply.github.com> Date: Mon, 26 Sep 2022 15:20:40 +0530 Subject: [PATCH 09/13] directory wise make flow Each checker have seperate directory wise make flow through main makefile --- ivl_uvm_tests/ivl_uvm_ovl_tests/Makefile | 17 ++++ ivl_uvm_tests/ivl_uvm_ovl_tests/README | 41 ++++++++ .../ivl_uvm_ovl_even_parity/Makefile | 19 ++++ .../ivl_uvm_ovl_even_parity/flist | 3 + .../ivl_uvm_ovl_even_parity_fail.sv | 78 +++++++++++++++ .../ivl_uvm_ovl_even_parity_pass.sv | 63 ++++++++++++ .../ivl_uvm_ovl_fifo_index/Makefile | 18 ++++ .../ivl_uvm_ovl_fifo_index/flist | 3 + .../ivl_uvm_ovl_fifo_index_fail.sv | 96 +++++++++++++++++++ .../ivl_uvm_ovl_fifo_index_pass.sv | 54 +++++++++++ .../ivl_uvm_ovl_win_change/Makefile | 18 ++++ .../ivl_uvm_ovl_win_change/flist | 3 + .../ivl_uvm_ovl_win_change_fail.sv | 96 +++++++++++++++++++ .../ivl_uvm_ovl_win_change_pass.sv | 85 ++++++++++++++++ .../ivl_uvm_ovl_win_unchange/Makefile | 18 ++++ .../ivl_uvm_ovl_win_unchange/flist | 3 + .../ivl_uvm_ovl_win_unchange_fail.sv | 75 +++++++++++++++ .../ivl_uvm_ovl_win_unchange_pass.sv | 75 +++++++++++++++ 18 files changed, 765 insertions(+) create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/Makefile create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/README create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/Makefile create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/flist create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/ivl_uvm_ovl_even_parity_fail.sv create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/ivl_uvm_ovl_even_parity_pass.sv create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/Makefile create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/flist create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/ivl_uvm_ovl_fifo_index_fail.sv create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/ivl_uvm_ovl_fifo_index_pass.sv create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/Makefile create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/flist create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/ivl_uvm_ovl_win_change_fail.sv create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/ivl_uvm_ovl_win_change_pass.sv create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/Makefile create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/flist create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_fail.sv create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_pass.sv diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/Makefile b/ivl_uvm_tests/ivl_uvm_ovl_tests/Makefile new file mode 100644 index 0000000..120f719 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/Makefile @@ -0,0 +1,17 @@ +SUBDIRS = $(shell ls -d */) +all: + for dir in $(SUBDIRS) ; do \ + make --no-print-directory -C $$dir ; \ + done + +clean: + for dir in $(SUBDIRS) ; do \ + make --no-print-directory -C $$dir clean;\ + done + +help: + for dir in $(SUBDIRS) ; do \ + make --no-print-directory -C $$dir help;\ + done + + \ No newline at end of file diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/README b/ivl_uvm_tests/ivl_uvm_ovl_tests/README new file mode 100644 index 0000000..ed05ddf --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/README @@ -0,0 +1,41 @@ +---------------->>>>>>>>>>>>>>>> Makefile Run flow +Main makefile as below path +/ivl_uvm-main/ivl_uvm_tests/ivl_uvm_ovl_tests/Makefile + +Main makefile will invoke each checker subdir makefile as below names +ivl_uvm_ovl_even_parity/Makefile + + + +---------------->>>>>>>>>>>>>>>> To Run all checker + +make all [this will run each chekcer makefiles (with pass and fail cases) ] +make clean[ clean all the dumps] +make help [this will show which are the targets for indiviadual checker] + +---------------->>>>>>>>>>>>>>>> To Run individual checker + +[1] ovl_even_parity_pass +% cd ivl_uvm_ovl_even_parity/ + +% ls +Makefile flist ivl_uvm_ovl_even_parity_fail.sv ivl_uvm_ovl_even_parity_pass.sv + +% make +rm -fr a.out *.log *.vcd tee +iverilog -g2012 -s test -I/C/ivl_uvm-main1_sep_dir/ivl_uvm-main/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_even_parity_pass.sv>& pass_comp.log +vvp a.out >& pass_run.log +iverilog -g2012 -s test -I/C/ivl_uvm-main1_sep_dir/ivl_uvm-main/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_even_parity_fail.sv >& fail_comp.log +vvp a.out >& fail_run.log +(Targets - clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_change_pass ovl_win_change_fail ) + + +---------------->>>>>>>>>>>>>>>> To see the waveform in GTK wave + +pacman -S mingw-w64-x86_64-gtkwave --> to install GTK wave + +then after running the test with make it will create a dump.vcd + +gtkwave -o -t des.stems dump.vcd des.sav + + diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/Makefile b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/Makefile new file mode 100644 index 0000000..59b7f18 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/Makefile @@ -0,0 +1,19 @@ +all: clean ovl_even_parity_pass ovl_even_parity_fail help + + +ovl_even_parity_pass: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_even_parity_pass.sv>& pass_comp.log + vvp a.out >& pass_run.log + +ovl_even_parity_fail: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_even_parity_fail.sv >& fail_comp.log + vvp a.out >& fail_run.log + +clean: + rm -fr a.out *.log *.vcd tee + +help: + @echo "(Targets - clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_change_pass ovl_win_change_fail )" + + + diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/flist b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/flist new file mode 100644 index 0000000..17f991f --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/flist @@ -0,0 +1,3 @@ +${IVL_UVM_HOME}/ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v +../ivl_uvm_ovl_clk_gen.sv +#../ivl_uvm_ovl_fifo_dut.sv diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/ivl_uvm_ovl_even_parity_fail.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/ivl_uvm_ovl_even_parity_fail.sv new file mode 100644 index 0000000..932b298 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/ivl_uvm_ovl_even_parity_fail.sv @@ -0,0 +1,78 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, wn, rn; + reg DATAIN; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_even_parity + ovl_even_parity u_ovl_even_parity ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .test_expr (DATAIN) + + ); + + + + +initial begin + reset = 0; wn = 0; rn = 0; + wait_clks(5); + + reset = 1; + wait_clks(5); + + + $display("Start testing"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 1"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 2"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 3"); + + + $display("real parity injecting 1"); + DATAIN = 1; + wait_clks(1); + + + $display("real parity injecting 2"); + DATAIN = 2; + wait_clks(1); + + $display("Real parity injecting 3"); + DATAIN = 99; + wait_clks(1); + + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/ivl_uvm_ovl_even_parity_pass.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/ivl_uvm_ovl_even_parity_pass.sv new file mode 100644 index 0000000..6203812 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/ivl_uvm_ovl_even_parity_pass.sv @@ -0,0 +1,63 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, wn, rn; + reg DATAIN; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_even_parity + ovl_even_parity u_ovl_even_parity ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .test_expr (DATAIN) + + ); + + + + +initial begin + reset = 0; wn = 0; rn = 0; + wait_clks(5); + + + + $display("Start testing"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 1"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 2"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 3"); + + + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/Makefile b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/Makefile new file mode 100644 index 0000000..4f9f83e --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/Makefile @@ -0,0 +1,18 @@ +all: clean ovl_fifo_index_pass ovl_fifo_index_fail help + +ovl_fifo_index_pass: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_fifo_index_pass.sv>& pass_comp.log + vvp a.out >& pass_run.log + +ovl_fifo_index_fail: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_fifo_index_fail.sv >& fail_comp.log + vvp a.out >& fail_run.log + +clean: + rm -fr a.out *.log *.vcd tee + +help: + @echo "(Targets - clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_change_pass ovl_win_change_fail )" + + + diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/flist b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/flist new file mode 100644 index 0000000..17f991f --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/flist @@ -0,0 +1,3 @@ +${IVL_UVM_HOME}/ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v +../ivl_uvm_ovl_clk_gen.sv +#../ivl_uvm_ovl_fifo_dut.sv diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/ivl_uvm_ovl_fifo_index_fail.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/ivl_uvm_ovl_fifo_index_fail.sv new file mode 100644 index 0000000..4616364 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/ivl_uvm_ovl_fifo_index_fail.sv @@ -0,0 +1,96 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, wn, rn; + reg [7:0] DATAIN; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_fifo_index + ovl_fifo_index u_ovl_fifo_index ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .push (wn), + .pop (rn) + ); + + // Instantiate OVL example - ovl_even_parity +// ovl_even_parity u_ovl_even_parity ( +// .clock (clk), +// .reset (reset), +// .enable (1'b1), +// .test_expr (DATAOUT[0]) +// +// ); + + + + +initial begin + reset = 0; wn = 0; rn = 0; + wait_clks(5); + + reset = 1; + wait_clks(5); + + + $display("Start testing"); + $display("Underflow injecting"); + wn = 0; rn = 1; + wait_clks(5); + + wn = 1; rn = 0; + wait_clks(5); + + $display("overflow injecting"); + wn = 1; rn = 0; + wait_clks(5); + + wn = 1; rn = 0; + wait_clks(5); + + wn = 1; rn = 0; + wait_clks(5); + + + wn = 1; rn = 0; + wait_clks(5); + + + wn = 1; rn = 0; + wait_clks(5); + + + wn = 1; rn = 0; + wait_clks(5); + + + wn = 1; rn = 0; + wait_clks(5); + + + wn = 1; rn = 0; + wait_clks(5); + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/ivl_uvm_ovl_fifo_index_pass.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/ivl_uvm_ovl_fifo_index_pass.sv new file mode 100644 index 0000000..5d0ea85 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/ivl_uvm_ovl_fifo_index_pass.sv @@ -0,0 +1,54 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, wn, rn; + reg [7:0] DATAIN; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_fifo_index + ovl_fifo_index u_ovl_fifo_index ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .push (wn), + .pop (rn) + ); + +initial begin + reset = 0; wn = 0; rn = 0; + wait_clks(5); + + reset = 1; + wait_clks(5); + + $display("Start testing"); + + $display(" Writing"); + + wn = 1; rn = 0; + wait_clks(1); + + + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/Makefile b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/Makefile new file mode 100644 index 0000000..5f5d2bd --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/Makefile @@ -0,0 +1,18 @@ +all: clean ovl_win_change_pass ovl_win_change_fail help + +ovl_win_change_pass: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_win_change_pass.sv>& pass_comp.log + vvp a.out >& pass_run.log + +ovl_win_change_fail: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_win_change_fail.sv>& fail_comp.log + vvp a.out >& fail_run.log + +clean: + rm -fr a.out *.log *.vcd tee + +help: + @echo "(Targets - clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_change_pass ovl_win_change_fail )" + + + diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/flist b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/flist new file mode 100644 index 0000000..17f991f --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/flist @@ -0,0 +1,3 @@ +${IVL_UVM_HOME}/ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v +../ivl_uvm_ovl_clk_gen.sv +#../ivl_uvm_ovl_fifo_dut.sv diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/ivl_uvm_ovl_win_change_fail.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/ivl_uvm_ovl_win_change_fail.sv new file mode 100644 index 0000000..a615a76 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/ivl_uvm_ovl_win_change_fail.sv @@ -0,0 +1,96 @@ +// This is linear queue / FIFO +// The queue length 1 +// CASES A ,C ,and D should expect as fail + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, rd,rd_ack,DATA; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_even_parity + ovl_win_change u_ovl_win_change ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .start_event(rd), + .test_expr (DATA), + .end_event(rd_ack) + + ); + + + + +initial begin + reset = 0; rd = 0; rd_ack = 0; + wait_clks(5); + + reset =1; + wait_clks(5); + + + + $display("Start testing"); + + $display("1 A with no change in data"); + + DATA = 0; rd =1; rd_ack =0; + wait_clks(1); + $display("A"); + + + DATA = 0; rd_ack =1; + wait_clks(1); + $display("2 A with no change in data"); + + + $display("1 B with change in data"); + DATA = 1; rd =1;rd_ack =0; + wait_clks(1); + $display("B"); + + DATA = 0; rd_ack =1; + wait_clks(1); + $display("2 B with change in data"); + + $display("1 C with no change in data"); + DATA = 1; rd =1;rd_ack =0; + wait_clks(1); + $display("C"); + + DATA = 1; rd_ack =1; + wait_clks(1); + $display("2 C with no change in data"); + + + $display("1 D with no change in data"); + DATA = 1; rd =1;rd_ack =0; + wait_clks(1); + $display("D"); + + DATA = 1; rd_ack =1; + wait_clks(1); + $display("2 D with no change in data"); + + + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/ivl_uvm_ovl_win_change_pass.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/ivl_uvm_ovl_win_change_pass.sv new file mode 100644 index 0000000..4d8a783 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/ivl_uvm_ovl_win_change_pass.sv @@ -0,0 +1,85 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, rd,rd_ack,DATA; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_even_parity + ovl_win_change u_ovl_win_change ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .start_event(rd), + .test_expr (DATA), + .end_event(rd_ack) + + ); + + + + +initial begin + reset = 0; rd = 0; rd_ack = 0; + wait_clks(5); + + reset =1; + wait_clks(5); + + + + $display("Start testing"); + + $display("1 A with change in data"); + + DATA = 1; rd =1; rd_ack =0; + wait_clks(1); + $display("A"); + + + DATA = 0; rd_ack =1; + wait_clks(1); + $display("2 A with change in data"); + + + $display("1 B with change in data"); + DATA = 1; rd =1;rd_ack =0; + wait_clks(1); + $display("B"); + + DATA = 0; rd_ack =1; + wait_clks(1); + $display("2 B with change in data"); + + $display("1 D with change in data"); + DATA = 1; rd =1;rd_ack =0; + wait_clks(1); + $display("D"); + + DATA = 0; rd_ack =1; + wait_clks(1); + $display("2 D with change in data"); + + + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/Makefile b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/Makefile new file mode 100644 index 0000000..e253a9c --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/Makefile @@ -0,0 +1,18 @@ +all: clean ovl_win_unchange_pass ovl_win_unchange_fail help + +ovl_win_unchange_pass: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_win_unchange_pass.sv>& pass_comp.log + vvp a.out >& pass_run.log + +ovl_win_unchange_fail: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_win_unchange_fail.sv>& fail_comp.log + vvp a.out >& fail_run.log + +clean: + rm -fr a.out *.log *.vcd tee + +help: + @echo "(Targets - clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_unchange_pass ovl_win_unchange_fail )" + + + diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/flist b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/flist new file mode 100644 index 0000000..17f991f --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/flist @@ -0,0 +1,3 @@ +${IVL_UVM_HOME}/ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v +../ivl_uvm_ovl_clk_gen.sv +#../ivl_uvm_ovl_fifo_dut.sv diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_fail.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_fail.sv new file mode 100644 index 0000000..ceab89d --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_fail.sv @@ -0,0 +1,75 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, rd,rd_ack,DATA; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_even_parity + ovl_win_unchange u_ovl_win_unchange ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .start_event(rd), + .test_expr (DATA), + .end_event(rd_ack) + + ); + + + + +initial begin + reset = 0; rd = 0; rd_ack = 0; + + + + + $display("Start testing"); + + DATA = 0; rd =0; rd_ack =0; + wait_clks(0); + + $display("1 A with change in data"); + + DATA = 1; rd =1; rd_ack =0; + wait_clks(5); + $display("A"); + + + DATA = 0; + wait_clks(2); + + $display("2 A with data changing "); + + DATA = 1; + wait_clks(2); + + rd_ack =1; + wait_clks(5); + + $display("3 A with change in data"); + + + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_pass.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_pass.sv new file mode 100644 index 0000000..ceab89d --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_pass.sv @@ -0,0 +1,75 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, rd,rd_ack,DATA; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_even_parity + ovl_win_unchange u_ovl_win_unchange ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .start_event(rd), + .test_expr (DATA), + .end_event(rd_ack) + + ); + + + + +initial begin + reset = 0; rd = 0; rd_ack = 0; + + + + + $display("Start testing"); + + DATA = 0; rd =0; rd_ack =0; + wait_clks(0); + + $display("1 A with change in data"); + + DATA = 1; rd =1; rd_ack =0; + wait_clks(5); + $display("A"); + + + DATA = 0; + wait_clks(2); + + $display("2 A with data changing "); + + DATA = 1; + wait_clks(2); + + rd_ack =1; + wait_clks(5); + + $display("3 A with change in data"); + + + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule From 6f346edbe258035c426656447c80a5c9a8341924 Mon Sep 17 00:00:00 2001 From: nipulkumar-11 <79196196+nipulkumar-11@users.noreply.github.com> Date: Mon, 26 Sep 2022 15:29:03 +0530 Subject: [PATCH 10/13] changed dir structure --- .../ivl_uvm_ovl_alw/Makefile | 23 +++++++++++-------- .../ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist | 1 + 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/Makefile b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/Makefile index 327771f..80c88f9 100644 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/Makefile +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/Makefile @@ -1,12 +1,17 @@ -all: - make --no-print-directory -f OVL_EVEN_PARITY - make --no-print-directory -f OVL_WIN_CHANGE - make --no-print-directory -f OVL_FIFO_INDEX +all: clean pass fail + +pass: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_a_alw_pass.sv >& pass_comp.log + #iverilog -s test -I../../ivl_uvm_std_ovl/ ../../ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v ivl_uvm_ovl_ex.sv |& tee comp.log + vvp a.out >& pass_run.log + +fail: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_a_alw_fail.sv >& fail_comp.log + vvp a.out >& fail_run.log + clean: - rm -fr a.out *.log *.vcd tee + rm -fr a.out *.log *.vcd tee + + -help: - make --no-print-directory -f OVL_EVEN_PARITY help - make --no-print-directory -f OVL_WIN_CHANGE help - make --no-print-directory -f OVL_FIFO_INDEX help \ No newline at end of file diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist index ef2d79b..17f991f 100644 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist @@ -1,2 +1,3 @@ ${IVL_UVM_HOME}/ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v ../ivl_uvm_ovl_clk_gen.sv +#../ivl_uvm_ovl_fifo_dut.sv From 9095b01723569e536d5f14f7d1e8a4d7cb6897c7 Mon Sep 17 00:00:00 2001 From: nipulkumar-11 <79196196+nipulkumar-11@users.noreply.github.com> Date: Mon, 26 Sep 2022 15:30:22 +0530 Subject: [PATCH 11/13] Delete ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw directory --- .../ivl_uvm_ovl_alw/Makefile | 17 ---- .../ivl_uvm_ovl_alw/OVL_EVEN_PARITY | 19 ---- .../ivl_uvm_ovl_alw/OVL_FIFO_INDEX | 18 ---- .../ivl_uvm_ovl_alw/OVL_WIN_CHANGE | 18 ---- .../ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README | 44 --------- .../ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist | 3 - .../ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_fail.sv | 51 ---------- .../ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_pass.sv | 73 -------------- .../ivl_uvm_ovl_even_parity_fail.sv | 78 --------------- .../ivl_uvm_ovl_even_parity_pass.sv | 63 ------------ .../ivl_uvm_ovl_fifo_index_fail.sv | 96 ------------------- .../ivl_uvm_ovl_fifo_index_pass.sv | 54 ----------- .../ivl_uvm_ovl_win_change_fail.sv | 96 ------------------- .../ivl_uvm_ovl_win_change_pass.sv | 85 ---------------- 14 files changed, 715 deletions(-) delete mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/Makefile delete mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_EVEN_PARITY delete mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_FIFO_INDEX delete mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_WIN_CHANGE delete mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README delete mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist delete mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_fail.sv delete mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_pass.sv delete mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_even_parity_fail.sv delete mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_even_parity_pass.sv delete mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_fifo_index_fail.sv delete mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_fifo_index_pass.sv delete mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_win_change_fail.sv delete mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_win_change_pass.sv diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/Makefile b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/Makefile deleted file mode 100644 index 80c88f9..0000000 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -all: clean pass fail - -pass: - iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_a_alw_pass.sv >& pass_comp.log - #iverilog -s test -I../../ivl_uvm_std_ovl/ ../../ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v ivl_uvm_ovl_ex.sv |& tee comp.log - vvp a.out >& pass_run.log - -fail: - iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_a_alw_fail.sv >& fail_comp.log - vvp a.out >& fail_run.log - - -clean: - rm -fr a.out *.log *.vcd tee - - - diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_EVEN_PARITY b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_EVEN_PARITY deleted file mode 100644 index 59b7f18..0000000 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_EVEN_PARITY +++ /dev/null @@ -1,19 +0,0 @@ -all: clean ovl_even_parity_pass ovl_even_parity_fail help - - -ovl_even_parity_pass: - iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_even_parity_pass.sv>& pass_comp.log - vvp a.out >& pass_run.log - -ovl_even_parity_fail: - iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_even_parity_fail.sv >& fail_comp.log - vvp a.out >& fail_run.log - -clean: - rm -fr a.out *.log *.vcd tee - -help: - @echo "(Targets - clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_change_pass ovl_win_change_fail )" - - - diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_FIFO_INDEX b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_FIFO_INDEX deleted file mode 100644 index 4f9f83e..0000000 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_FIFO_INDEX +++ /dev/null @@ -1,18 +0,0 @@ -all: clean ovl_fifo_index_pass ovl_fifo_index_fail help - -ovl_fifo_index_pass: - iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_fifo_index_pass.sv>& pass_comp.log - vvp a.out >& pass_run.log - -ovl_fifo_index_fail: - iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_fifo_index_fail.sv >& fail_comp.log - vvp a.out >& fail_run.log - -clean: - rm -fr a.out *.log *.vcd tee - -help: - @echo "(Targets - clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_change_pass ovl_win_change_fail )" - - - diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_WIN_CHANGE b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_WIN_CHANGE deleted file mode 100644 index 5f5d2bd..0000000 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/OVL_WIN_CHANGE +++ /dev/null @@ -1,18 +0,0 @@ -all: clean ovl_win_change_pass ovl_win_change_fail help - -ovl_win_change_pass: - iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_win_change_pass.sv>& pass_comp.log - vvp a.out >& pass_run.log - -ovl_win_change_fail: - iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_win_change_fail.sv>& fail_comp.log - vvp a.out >& fail_run.log - -clean: - rm -fr a.out *.log *.vcd tee - -help: - @echo "(Targets - clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_change_pass ovl_win_change_fail )" - - - diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README deleted file mode 100644 index 31f1f40..0000000 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/README +++ /dev/null @@ -1,44 +0,0 @@ ----------------->>>>>>>>>>>>>>>> Makefile flow -main makefile - Makefile - -Main will invoke each checker makefile as below names -OVL_EVEN_PARITY -OVL_WIN_CHANGE -OVL_FIFO_INDEX - - ----------------->>>>>>>>>>>>>>>> To Run all checker - -make all [this will run each chekcer makefiles (with pass and fail cases) ] -make help [this will show which are the targets for indiviadual checker] - ----------------->>>>>>>>>>>>>>>> To Run individual checker - -[1] ovl_fifo_index_pass -% make -f OVL_FIFO_INDEX ovl_fifo_index_pass -iverilog -g2012 -s test -I/c/ivl_uvm-main1/ivl_uvm-main/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_fifo_index_pass.sv>& pass_comp.log -vvp a.out >& pass_run.log - -% cat pass_run.log -OVL_NOTE: V2.8: OVL_FIFO_INDEX initialized @ test.u_ovl_fifo_index.ovl_init_msg_t Severity: 1, Message: VIOLATION -test.u_clk_100 FREQ_IN_MHZ = 100.000 MHz -test.u_clk_100 PERIOD = 10.000 ns -VCD info: dumpfile dump.vcd opened for output. -Start testing - Writing -ivl_uvm_ovl_fifo_index_pass.sv:44: $finish called at 110000000 (1fs) - -[2] ovl_fifo_index_fail -% make -f OVL_FIFO_INDEX ovl_fifo_index_fail -iverilog -g2012 -s test -I/c/ivl_uvm-main1/ivl_uvm-main/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_fifo_index_fail.sv >& fail_comp.log -vvp a.out >& fail_run.log - ----------------->>>>>>>>>>>>>>>> To see the waveform in GTK wave - -pacman -S mingw-w64-x86_64-gtkwave --> to install GTK wave - -then after running the test with make it will create a dump.vcd - -gtkwave -o -t des.stems dump.vcd des.sav - - diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist deleted file mode 100644 index 17f991f..0000000 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist +++ /dev/null @@ -1,3 +0,0 @@ -${IVL_UVM_HOME}/ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v -../ivl_uvm_ovl_clk_gen.sv -#../ivl_uvm_ovl_fifo_dut.sv diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_fail.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_fail.sv deleted file mode 100644 index 76fcd42..0000000 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_fail.sv +++ /dev/null @@ -1,51 +0,0 @@ -`timescale 1ns/1ns - -module test; - - wire clk; - reg rst_n; - reg alw_high_sig; - - // Instantiate OVL example - ovl_always u_ovl_always ( - .clock (clk), - .reset (rst_n), - .enable (1'b1), - .test_expr (alw_high_sig) - ); - - initial begin - // Dump waves - $dumpfile("dump.vcd"); - $dumpvars(1, test); - - // Initialize values. - rst_n = 0; - alw_high_sig = 0; - - $display("ovl_always does not fire at rst_n"); - alw_high_sig = 1; - wait_clks(5); - - rst_n = 1; - wait_clks(5); - $display("Out of reset"); - - alw_high_sig = 0; - $display({"ovl_always expect 1- OVL_ERROR ", - "when alw_high_sig is FALSE"}); - - - wait_clks(10); - - $finish; - end - - task wait_clks (input int num_clks = 1); - repeat (num_clks) @(posedge clk); - endtask : wait_clks - - ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); - -endmodule - diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_pass.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_pass.sv deleted file mode 100644 index b1a40ca..0000000 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_pass.sv +++ /dev/null @@ -1,73 +0,0 @@ -`timescale 1ns/1ns - -module test; - - wire clk; - reg rst_n; - reg alw_high_sig; - - logic wr_val, wr_done; - logic [7:0] arb_gnt_vec; - - // Check wr_val is not same as wr_done - ovl_always u_chk_mutex_wr_valid ( - .clock (clk), - .reset (rst_n), - .enable (1'b1), - .test_expr (wr_val != wr_done) - ); - - // simple signal check OVL - ovl_always u_ovl_always ( - .clock (clk), - .reset (rst_n), - .enable (1'b1), - .test_expr (alw_high_sig) - ); - - // use function - ovl_always u_ovl_a_fn ( - .clock (clk), - .reset (rst_n), - .enable (1'b1), - .test_expr ( ($countones (arb_gnt_vec) <= 1)) - ); - - initial begin - // Dump waves - $dumpfile("dump.vcd"); - $dumpvars(1, test); - - // Initialize values. - rst_n = 0; - alw_high_sig = 0; - arb_gnt_vec = 0; - wr_val = 0; - wr_done = 1; - - $display("ovl_always does not fire at rst_n"); - alw_high_sig = 1; - wait_clks(5); - - rst_n = 1; - wait_clks(5); - $display("Out of reset"); - - alw_high_sig = 1; - $display({"ovl_always does not fire ", - "when alw_high_sig is FALSE"}); - - wait_clks(10); - - $finish; - end - - task wait_clks (input int num_clks = 1); - repeat (num_clks) @(posedge clk); - endtask : wait_clks - - ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); - -endmodule - - diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_even_parity_fail.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_even_parity_fail.sv deleted file mode 100644 index 932b298..0000000 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_even_parity_fail.sv +++ /dev/null @@ -1,78 +0,0 @@ -// This is linear queue / FIFO -// The queue length 1 - -`timescale 1ns/1ns - -// TB -module test; - - logic clk, reset, wn, rn; - reg DATAIN; - - //enabling the wave dump - initial begin - $dumpfile("dump.vcd"); - $dumpvars(0, test); - - end - - // Instantiate OVL example - ovl_even_parity - ovl_even_parity u_ovl_even_parity ( - .clock (clk), - .reset (reset), - .enable (1'b1), - .test_expr (DATAIN) - - ); - - - - -initial begin - reset = 0; wn = 0; rn = 0; - wait_clks(5); - - reset = 1; - wait_clks(5); - - - $display("Start testing"); - - DATAIN = 0; - wait_clks(1); - $display("done parity injecting 1"); - - DATAIN = 0; - wait_clks(1); - $display("done parity injecting 2"); - - DATAIN = 0; - wait_clks(1); - $display("done parity injecting 3"); - - - $display("real parity injecting 1"); - DATAIN = 1; - wait_clks(1); - - - $display("real parity injecting 2"); - DATAIN = 2; - wait_clks(1); - - $display("Real parity injecting 3"); - DATAIN = 99; - wait_clks(1); - - - $finish; - -end - - task wait_clks(input int num_clks = 1); - repeat (num_clks) @(posedge clk); - endtask : wait_clks - - ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); - -endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_even_parity_pass.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_even_parity_pass.sv deleted file mode 100644 index 6203812..0000000 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_even_parity_pass.sv +++ /dev/null @@ -1,63 +0,0 @@ -// This is linear queue / FIFO -// The queue length 1 - -`timescale 1ns/1ns - -// TB -module test; - - logic clk, reset, wn, rn; - reg DATAIN; - - //enabling the wave dump - initial begin - $dumpfile("dump.vcd"); - $dumpvars(0, test); - - end - - // Instantiate OVL example - ovl_even_parity - ovl_even_parity u_ovl_even_parity ( - .clock (clk), - .reset (reset), - .enable (1'b1), - .test_expr (DATAIN) - - ); - - - - -initial begin - reset = 0; wn = 0; rn = 0; - wait_clks(5); - - - - $display("Start testing"); - - DATAIN = 0; - wait_clks(1); - $display("done parity injecting 1"); - - DATAIN = 0; - wait_clks(1); - $display("done parity injecting 2"); - - DATAIN = 0; - wait_clks(1); - $display("done parity injecting 3"); - - - - $finish; - -end - - task wait_clks(input int num_clks = 1); - repeat (num_clks) @(posedge clk); - endtask : wait_clks - - ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); - -endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_fifo_index_fail.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_fifo_index_fail.sv deleted file mode 100644 index 4616364..0000000 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_fifo_index_fail.sv +++ /dev/null @@ -1,96 +0,0 @@ -// This is linear queue / FIFO -// The queue length 1 - -`timescale 1ns/1ns - -// TB -module test; - - logic clk, reset, wn, rn; - reg [7:0] DATAIN; - - //enabling the wave dump - initial begin - $dumpfile("dump.vcd"); - $dumpvars(0, test); - - end - - // Instantiate OVL example - ovl_fifo_index - ovl_fifo_index u_ovl_fifo_index ( - .clock (clk), - .reset (reset), - .enable (1'b1), - .push (wn), - .pop (rn) - ); - - // Instantiate OVL example - ovl_even_parity -// ovl_even_parity u_ovl_even_parity ( -// .clock (clk), -// .reset (reset), -// .enable (1'b1), -// .test_expr (DATAOUT[0]) -// -// ); - - - - -initial begin - reset = 0; wn = 0; rn = 0; - wait_clks(5); - - reset = 1; - wait_clks(5); - - - $display("Start testing"); - $display("Underflow injecting"); - wn = 0; rn = 1; - wait_clks(5); - - wn = 1; rn = 0; - wait_clks(5); - - $display("overflow injecting"); - wn = 1; rn = 0; - wait_clks(5); - - wn = 1; rn = 0; - wait_clks(5); - - wn = 1; rn = 0; - wait_clks(5); - - - wn = 1; rn = 0; - wait_clks(5); - - - wn = 1; rn = 0; - wait_clks(5); - - - wn = 1; rn = 0; - wait_clks(5); - - - wn = 1; rn = 0; - wait_clks(5); - - - wn = 1; rn = 0; - wait_clks(5); - - $finish; - -end - - task wait_clks(input int num_clks = 1); - repeat (num_clks) @(posedge clk); - endtask : wait_clks - - ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); - -endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_fifo_index_pass.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_fifo_index_pass.sv deleted file mode 100644 index 5d0ea85..0000000 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_fifo_index_pass.sv +++ /dev/null @@ -1,54 +0,0 @@ -// This is linear queue / FIFO -// The queue length 1 - -`timescale 1ns/1ns - -// TB -module test; - - logic clk, reset, wn, rn; - reg [7:0] DATAIN; - - //enabling the wave dump - initial begin - $dumpfile("dump.vcd"); - $dumpvars(0, test); - - end - - // Instantiate OVL example - ovl_fifo_index - ovl_fifo_index u_ovl_fifo_index ( - .clock (clk), - .reset (reset), - .enable (1'b1), - .push (wn), - .pop (rn) - ); - -initial begin - reset = 0; wn = 0; rn = 0; - wait_clks(5); - - reset = 1; - wait_clks(5); - - $display("Start testing"); - - $display(" Writing"); - - wn = 1; rn = 0; - wait_clks(1); - - - - $finish; - -end - - task wait_clks(input int num_clks = 1); - repeat (num_clks) @(posedge clk); - endtask : wait_clks - - ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); - -endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_win_change_fail.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_win_change_fail.sv deleted file mode 100644 index a615a76..0000000 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_win_change_fail.sv +++ /dev/null @@ -1,96 +0,0 @@ -// This is linear queue / FIFO -// The queue length 1 -// CASES A ,C ,and D should expect as fail - -`timescale 1ns/1ns - -// TB -module test; - - logic clk, reset, rd,rd_ack,DATA; - - //enabling the wave dump - initial begin - $dumpfile("dump.vcd"); - $dumpvars(0, test); - - end - - // Instantiate OVL example - ovl_even_parity - ovl_win_change u_ovl_win_change ( - .clock (clk), - .reset (reset), - .enable (1'b1), - .start_event(rd), - .test_expr (DATA), - .end_event(rd_ack) - - ); - - - - -initial begin - reset = 0; rd = 0; rd_ack = 0; - wait_clks(5); - - reset =1; - wait_clks(5); - - - - $display("Start testing"); - - $display("1 A with no change in data"); - - DATA = 0; rd =1; rd_ack =0; - wait_clks(1); - $display("A"); - - - DATA = 0; rd_ack =1; - wait_clks(1); - $display("2 A with no change in data"); - - - $display("1 B with change in data"); - DATA = 1; rd =1;rd_ack =0; - wait_clks(1); - $display("B"); - - DATA = 0; rd_ack =1; - wait_clks(1); - $display("2 B with change in data"); - - $display("1 C with no change in data"); - DATA = 1; rd =1;rd_ack =0; - wait_clks(1); - $display("C"); - - DATA = 1; rd_ack =1; - wait_clks(1); - $display("2 C with no change in data"); - - - $display("1 D with no change in data"); - DATA = 1; rd =1;rd_ack =0; - wait_clks(1); - $display("D"); - - DATA = 1; rd_ack =1; - wait_clks(1); - $display("2 D with no change in data"); - - - - $finish; - -end - - task wait_clks(input int num_clks = 1); - repeat (num_clks) @(posedge clk); - endtask : wait_clks - - ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); - -endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_win_change_pass.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_win_change_pass.sv deleted file mode 100644 index 4d8a783..0000000 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_win_change_pass.sv +++ /dev/null @@ -1,85 +0,0 @@ -// This is linear queue / FIFO -// The queue length 1 - -`timescale 1ns/1ns - -// TB -module test; - - logic clk, reset, rd,rd_ack,DATA; - - //enabling the wave dump - initial begin - $dumpfile("dump.vcd"); - $dumpvars(0, test); - - end - - // Instantiate OVL example - ovl_even_parity - ovl_win_change u_ovl_win_change ( - .clock (clk), - .reset (reset), - .enable (1'b1), - .start_event(rd), - .test_expr (DATA), - .end_event(rd_ack) - - ); - - - - -initial begin - reset = 0; rd = 0; rd_ack = 0; - wait_clks(5); - - reset =1; - wait_clks(5); - - - - $display("Start testing"); - - $display("1 A with change in data"); - - DATA = 1; rd =1; rd_ack =0; - wait_clks(1); - $display("A"); - - - DATA = 0; rd_ack =1; - wait_clks(1); - $display("2 A with change in data"); - - - $display("1 B with change in data"); - DATA = 1; rd =1;rd_ack =0; - wait_clks(1); - $display("B"); - - DATA = 0; rd_ack =1; - wait_clks(1); - $display("2 B with change in data"); - - $display("1 D with change in data"); - DATA = 1; rd =1;rd_ack =0; - wait_clks(1); - $display("D"); - - DATA = 0; rd_ack =1; - wait_clks(1); - $display("2 D with change in data"); - - - - $finish; - -end - - task wait_clks(input int num_clks = 1); - repeat (num_clks) @(posedge clk); - endtask : wait_clks - - ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); - -endmodule From b92f17fc15a99b39e46af402d486bac8cf096dff Mon Sep 17 00:00:00 2001 From: nipulkumar-11 <79196196+nipulkumar-11@users.noreply.github.com> Date: Mon, 26 Sep 2022 15:30:57 +0530 Subject: [PATCH 12/13] undo dir --- .../ivl_uvm_ovl_alw/Makefile | 17 +++++ .../ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist | 3 + .../ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_fail.sv | 51 +++++++++++++ .../ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_pass.sv | 73 +++++++++++++++++++ 4 files changed, 144 insertions(+) create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/Makefile create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_fail.sv create mode 100644 ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_pass.sv diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/Makefile b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/Makefile new file mode 100644 index 0000000..80c88f9 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/Makefile @@ -0,0 +1,17 @@ +all: clean pass fail + +pass: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_a_alw_pass.sv >& pass_comp.log + #iverilog -s test -I../../ivl_uvm_std_ovl/ ../../ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v ivl_uvm_ovl_ex.sv |& tee comp.log + vvp a.out >& pass_run.log + +fail: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_a_alw_fail.sv >& fail_comp.log + vvp a.out >& fail_run.log + + +clean: + rm -fr a.out *.log *.vcd tee + + + diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist new file mode 100644 index 0000000..17f991f --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist @@ -0,0 +1,3 @@ +${IVL_UVM_HOME}/ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v +../ivl_uvm_ovl_clk_gen.sv +#../ivl_uvm_ovl_fifo_dut.sv diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_fail.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_fail.sv new file mode 100644 index 0000000..76fcd42 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_fail.sv @@ -0,0 +1,51 @@ +`timescale 1ns/1ns + +module test; + + wire clk; + reg rst_n; + reg alw_high_sig; + + // Instantiate OVL example + ovl_always u_ovl_always ( + .clock (clk), + .reset (rst_n), + .enable (1'b1), + .test_expr (alw_high_sig) + ); + + initial begin + // Dump waves + $dumpfile("dump.vcd"); + $dumpvars(1, test); + + // Initialize values. + rst_n = 0; + alw_high_sig = 0; + + $display("ovl_always does not fire at rst_n"); + alw_high_sig = 1; + wait_clks(5); + + rst_n = 1; + wait_clks(5); + $display("Out of reset"); + + alw_high_sig = 0; + $display({"ovl_always expect 1- OVL_ERROR ", + "when alw_high_sig is FALSE"}); + + + wait_clks(10); + + $finish; + end + + task wait_clks (input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule + diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_pass.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_pass.sv new file mode 100644 index 0000000..b1a40ca --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/ivl_uvm_ovl_a_alw_pass.sv @@ -0,0 +1,73 @@ +`timescale 1ns/1ns + +module test; + + wire clk; + reg rst_n; + reg alw_high_sig; + + logic wr_val, wr_done; + logic [7:0] arb_gnt_vec; + + // Check wr_val is not same as wr_done + ovl_always u_chk_mutex_wr_valid ( + .clock (clk), + .reset (rst_n), + .enable (1'b1), + .test_expr (wr_val != wr_done) + ); + + // simple signal check OVL + ovl_always u_ovl_always ( + .clock (clk), + .reset (rst_n), + .enable (1'b1), + .test_expr (alw_high_sig) + ); + + // use function + ovl_always u_ovl_a_fn ( + .clock (clk), + .reset (rst_n), + .enable (1'b1), + .test_expr ( ($countones (arb_gnt_vec) <= 1)) + ); + + initial begin + // Dump waves + $dumpfile("dump.vcd"); + $dumpvars(1, test); + + // Initialize values. + rst_n = 0; + alw_high_sig = 0; + arb_gnt_vec = 0; + wr_val = 0; + wr_done = 1; + + $display("ovl_always does not fire at rst_n"); + alw_high_sig = 1; + wait_clks(5); + + rst_n = 1; + wait_clks(5); + $display("Out of reset"); + + alw_high_sig = 1; + $display({"ovl_always does not fire ", + "when alw_high_sig is FALSE"}); + + wait_clks(10); + + $finish; + end + + task wait_clks (input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule + + From 392b859c64ebb6b45b0136e008e32af0cbc2850f Mon Sep 17 00:00:00 2001 From: nipulkumar-11 <79196196+nipulkumar-11@users.noreply.github.com> Date: Thu, 29 Sep 2022 18:13:02 +0530 Subject: [PATCH 13/13] update update - proper scenario driven --- .../ivl_uvm_ovl_win_unchange_fail.sv | 76 ++++++++++++++----- .../ivl_uvm_ovl_win_unchange_pass.sv | 67 +++++++++++----- 2 files changed, 104 insertions(+), 39 deletions(-) diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_fail.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_fail.sv index ceab89d..584fcee 100644 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_fail.sv +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_fail.sv @@ -6,17 +6,12 @@ // TB module test; - logic clk, reset, rd,rd_ack,DATA; + logic clk, reset, rd,rd_ack; + reg [3:0]DATA; - //enabling the wave dump - initial begin - $dumpfile("dump.vcd"); - $dumpvars(0, test); - - end // Instantiate OVL example - ovl_even_parity - ovl_win_unchange u_ovl_win_unchange ( + ovl_win_unchange #( .width(4)) u_ovl_win_unchange ( .clock (clk), .reset (reset), .enable (1'b1), @@ -27,40 +22,85 @@ module test; ); + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end initial begin reset = 0; rd = 0; rd_ack = 0; - + wait_clks(5); - + reset = 1; + wait_clks(5); $display("Start testing"); DATA = 0; rd =0; rd_ack =0; - wait_clks(0); + wait_clks(5); +// A $display("1 A with change in data"); - DATA = 1; rd =1; rd_ack =0; + DATA = 4'b1111; rd =1; rd_ack =0; wait_clks(5); $display("A"); - DATA = 0; - wait_clks(2); + DATA = 4'b1110; + wait_clks(5); + + rd_ack =1; + wait_clks(5); $display("2 A with data changing "); - DATA = 1; - wait_clks(2); - +// B + + rd = 0; rd_ack =0; + wait_clks(5); + + $display("1 B with NOT change in data"); + + DATA = 4'b1100; rd =1; rd_ack =0; + wait_clks(5); + $display("B"); + + + DATA = 4'b1100; + wait_clks(5); + rd_ack =1; wait_clks(5); - $display("3 A with change in data"); + $display("2 B with NOT Data changing "); +// C + DATA = 0; rd =0; rd_ack =0; + wait_clks(5); + + $display("1 C with change in data"); + + DATA = 4'b0011; rd =1; rd_ack =0; + wait_clks(5); + $display("C"); + + + DATA = 4'b1110; + wait_clks(5); + + rd_ack =1; + wait_clks(5); + + $display("2 C with data changing "); + + + rd = 0; rd_ack =0; + wait_clks(5); $finish; diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_pass.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_pass.sv index ceab89d..1ae031a 100644 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_pass.sv +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_pass.sv @@ -6,17 +6,12 @@ // TB module test; - logic clk, reset, rd,rd_ack,DATA; + logic clk, reset, rd,rd_ack; + reg [3:0]DATA; - //enabling the wave dump - initial begin - $dumpfile("dump.vcd"); - $dumpvars(0, test); - - end // Instantiate OVL example - ovl_even_parity - ovl_win_unchange u_ovl_win_unchange ( + ovl_win_unchange #( .width(4)) u_ovl_win_unchange ( .clock (clk), .reset (reset), .enable (1'b1), @@ -27,40 +22,70 @@ module test; ); + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end initial begin reset = 0; rd = 0; rd_ack = 0; - + wait_clks(5); - + reset = 1; + wait_clks(5); $display("Start testing"); DATA = 0; rd =0; rd_ack =0; - wait_clks(0); + wait_clks(5); - $display("1 A with change in data"); - DATA = 1; rd =1; rd_ack =0; +// B + + rd = 0; rd_ack =0; wait_clks(5); - $display("A"); + + $display("1 B with NOT change in data"); + DATA = 4'b1100; rd =1; rd_ack =0; + wait_clks(5); + $display("B"); - DATA = 0; - wait_clks(2); - $display("2 A with data changing "); + DATA = 4'b1100; + wait_clks(5); - DATA = 1; - wait_clks(2); - rd_ack =1; wait_clks(5); - $display("3 A with change in data"); + $display("2 B with NOT Data changing "); + +// C + + DATA = 0; rd =0; rd_ack =0; + wait_clks(5); + + $display("1 C with NOT change in data"); + + DATA = 4'b0011; rd =1; rd_ack =0; + wait_clks(5); + $display("C"); + DATA = 4'b0011; + wait_clks(5); + + rd_ack =1; + wait_clks(5); + + $display("2 C with NOT data changing "); + + + rd = 0; rd_ack =0; + wait_clks(5); $finish;