diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/Makefile b/ivl_uvm_tests/ivl_uvm_ovl_tests/Makefile new file mode 100644 index 0000000..120f719 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/Makefile @@ -0,0 +1,17 @@ +SUBDIRS = $(shell ls -d */) +all: + for dir in $(SUBDIRS) ; do \ + make --no-print-directory -C $$dir ; \ + done + +clean: + for dir in $(SUBDIRS) ; do \ + make --no-print-directory -C $$dir clean;\ + done + +help: + for dir in $(SUBDIRS) ; do \ + make --no-print-directory -C $$dir help;\ + done + + \ No newline at end of file diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/README b/ivl_uvm_tests/ivl_uvm_ovl_tests/README new file mode 100644 index 0000000..ed05ddf --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/README @@ -0,0 +1,41 @@ +---------------->>>>>>>>>>>>>>>> Makefile Run flow +Main makefile as below path +/ivl_uvm-main/ivl_uvm_tests/ivl_uvm_ovl_tests/Makefile + +Main makefile will invoke each checker subdir makefile as below names +ivl_uvm_ovl_even_parity/Makefile + + + +---------------->>>>>>>>>>>>>>>> To Run all checker + +make all [this will run each chekcer makefiles (with pass and fail cases) ] +make clean[ clean all the dumps] +make help [this will show which are the targets for indiviadual checker] + +---------------->>>>>>>>>>>>>>>> To Run individual checker + +[1] ovl_even_parity_pass +% cd ivl_uvm_ovl_even_parity/ + +% ls +Makefile flist ivl_uvm_ovl_even_parity_fail.sv ivl_uvm_ovl_even_parity_pass.sv + +% make +rm -fr a.out *.log *.vcd tee +iverilog -g2012 -s test -I/C/ivl_uvm-main1_sep_dir/ivl_uvm-main/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_even_parity_pass.sv>& pass_comp.log +vvp a.out >& pass_run.log +iverilog -g2012 -s test -I/C/ivl_uvm-main1_sep_dir/ivl_uvm-main/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_even_parity_fail.sv >& fail_comp.log +vvp a.out >& fail_run.log +(Targets - clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_change_pass ovl_win_change_fail ) + + +---------------->>>>>>>>>>>>>>>> To see the waveform in GTK wave + +pacman -S mingw-w64-x86_64-gtkwave --> to install GTK wave + +then after running the test with make it will create a dump.vcd + +gtkwave -o -t des.stems dump.vcd des.sav + + diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist index ef2d79b..17f991f 100644 --- a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_alw/flist @@ -1,2 +1,3 @@ ${IVL_UVM_HOME}/ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v ../ivl_uvm_ovl_clk_gen.sv +#../ivl_uvm_ovl_fifo_dut.sv diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/Makefile b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/Makefile new file mode 100644 index 0000000..59b7f18 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/Makefile @@ -0,0 +1,19 @@ +all: clean ovl_even_parity_pass ovl_even_parity_fail help + + +ovl_even_parity_pass: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_even_parity_pass.sv>& pass_comp.log + vvp a.out >& pass_run.log + +ovl_even_parity_fail: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_even_parity_fail.sv >& fail_comp.log + vvp a.out >& fail_run.log + +clean: + rm -fr a.out *.log *.vcd tee + +help: + @echo "(Targets - clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_change_pass ovl_win_change_fail )" + + + diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/flist b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/flist new file mode 100644 index 0000000..17f991f --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/flist @@ -0,0 +1,3 @@ +${IVL_UVM_HOME}/ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v +../ivl_uvm_ovl_clk_gen.sv +#../ivl_uvm_ovl_fifo_dut.sv diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/ivl_uvm_ovl_even_parity_fail.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/ivl_uvm_ovl_even_parity_fail.sv new file mode 100644 index 0000000..932b298 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/ivl_uvm_ovl_even_parity_fail.sv @@ -0,0 +1,78 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, wn, rn; + reg DATAIN; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_even_parity + ovl_even_parity u_ovl_even_parity ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .test_expr (DATAIN) + + ); + + + + +initial begin + reset = 0; wn = 0; rn = 0; + wait_clks(5); + + reset = 1; + wait_clks(5); + + + $display("Start testing"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 1"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 2"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 3"); + + + $display("real parity injecting 1"); + DATAIN = 1; + wait_clks(1); + + + $display("real parity injecting 2"); + DATAIN = 2; + wait_clks(1); + + $display("Real parity injecting 3"); + DATAIN = 99; + wait_clks(1); + + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/ivl_uvm_ovl_even_parity_pass.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/ivl_uvm_ovl_even_parity_pass.sv new file mode 100644 index 0000000..6203812 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_even_parity/ivl_uvm_ovl_even_parity_pass.sv @@ -0,0 +1,63 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, wn, rn; + reg DATAIN; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_even_parity + ovl_even_parity u_ovl_even_parity ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .test_expr (DATAIN) + + ); + + + + +initial begin + reset = 0; wn = 0; rn = 0; + wait_clks(5); + + + + $display("Start testing"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 1"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 2"); + + DATAIN = 0; + wait_clks(1); + $display("done parity injecting 3"); + + + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/Makefile b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/Makefile new file mode 100644 index 0000000..4f9f83e --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/Makefile @@ -0,0 +1,18 @@ +all: clean ovl_fifo_index_pass ovl_fifo_index_fail help + +ovl_fifo_index_pass: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_fifo_index_pass.sv>& pass_comp.log + vvp a.out >& pass_run.log + +ovl_fifo_index_fail: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_fifo_index_fail.sv >& fail_comp.log + vvp a.out >& fail_run.log + +clean: + rm -fr a.out *.log *.vcd tee + +help: + @echo "(Targets - clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_change_pass ovl_win_change_fail )" + + + diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/flist b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/flist new file mode 100644 index 0000000..17f991f --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/flist @@ -0,0 +1,3 @@ +${IVL_UVM_HOME}/ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v +../ivl_uvm_ovl_clk_gen.sv +#../ivl_uvm_ovl_fifo_dut.sv diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/ivl_uvm_ovl_fifo_index_fail.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/ivl_uvm_ovl_fifo_index_fail.sv new file mode 100644 index 0000000..4616364 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/ivl_uvm_ovl_fifo_index_fail.sv @@ -0,0 +1,96 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, wn, rn; + reg [7:0] DATAIN; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_fifo_index + ovl_fifo_index u_ovl_fifo_index ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .push (wn), + .pop (rn) + ); + + // Instantiate OVL example - ovl_even_parity +// ovl_even_parity u_ovl_even_parity ( +// .clock (clk), +// .reset (reset), +// .enable (1'b1), +// .test_expr (DATAOUT[0]) +// +// ); + + + + +initial begin + reset = 0; wn = 0; rn = 0; + wait_clks(5); + + reset = 1; + wait_clks(5); + + + $display("Start testing"); + $display("Underflow injecting"); + wn = 0; rn = 1; + wait_clks(5); + + wn = 1; rn = 0; + wait_clks(5); + + $display("overflow injecting"); + wn = 1; rn = 0; + wait_clks(5); + + wn = 1; rn = 0; + wait_clks(5); + + wn = 1; rn = 0; + wait_clks(5); + + + wn = 1; rn = 0; + wait_clks(5); + + + wn = 1; rn = 0; + wait_clks(5); + + + wn = 1; rn = 0; + wait_clks(5); + + + wn = 1; rn = 0; + wait_clks(5); + + + wn = 1; rn = 0; + wait_clks(5); + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/ivl_uvm_ovl_fifo_index_pass.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/ivl_uvm_ovl_fifo_index_pass.sv new file mode 100644 index 0000000..5d0ea85 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_fifo_index/ivl_uvm_ovl_fifo_index_pass.sv @@ -0,0 +1,54 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, wn, rn; + reg [7:0] DATAIN; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_fifo_index + ovl_fifo_index u_ovl_fifo_index ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .push (wn), + .pop (rn) + ); + +initial begin + reset = 0; wn = 0; rn = 0; + wait_clks(5); + + reset = 1; + wait_clks(5); + + $display("Start testing"); + + $display(" Writing"); + + wn = 1; rn = 0; + wait_clks(1); + + + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/Makefile b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/Makefile new file mode 100644 index 0000000..5f5d2bd --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/Makefile @@ -0,0 +1,18 @@ +all: clean ovl_win_change_pass ovl_win_change_fail help + +ovl_win_change_pass: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_win_change_pass.sv>& pass_comp.log + vvp a.out >& pass_run.log + +ovl_win_change_fail: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_win_change_fail.sv>& fail_comp.log + vvp a.out >& fail_run.log + +clean: + rm -fr a.out *.log *.vcd tee + +help: + @echo "(Targets - clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_change_pass ovl_win_change_fail )" + + + diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/flist b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/flist new file mode 100644 index 0000000..17f991f --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/flist @@ -0,0 +1,3 @@ +${IVL_UVM_HOME}/ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v +../ivl_uvm_ovl_clk_gen.sv +#../ivl_uvm_ovl_fifo_dut.sv diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/ivl_uvm_ovl_win_change_fail.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/ivl_uvm_ovl_win_change_fail.sv new file mode 100644 index 0000000..a615a76 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/ivl_uvm_ovl_win_change_fail.sv @@ -0,0 +1,96 @@ +// This is linear queue / FIFO +// The queue length 1 +// CASES A ,C ,and D should expect as fail + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, rd,rd_ack,DATA; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_even_parity + ovl_win_change u_ovl_win_change ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .start_event(rd), + .test_expr (DATA), + .end_event(rd_ack) + + ); + + + + +initial begin + reset = 0; rd = 0; rd_ack = 0; + wait_clks(5); + + reset =1; + wait_clks(5); + + + + $display("Start testing"); + + $display("1 A with no change in data"); + + DATA = 0; rd =1; rd_ack =0; + wait_clks(1); + $display("A"); + + + DATA = 0; rd_ack =1; + wait_clks(1); + $display("2 A with no change in data"); + + + $display("1 B with change in data"); + DATA = 1; rd =1;rd_ack =0; + wait_clks(1); + $display("B"); + + DATA = 0; rd_ack =1; + wait_clks(1); + $display("2 B with change in data"); + + $display("1 C with no change in data"); + DATA = 1; rd =1;rd_ack =0; + wait_clks(1); + $display("C"); + + DATA = 1; rd_ack =1; + wait_clks(1); + $display("2 C with no change in data"); + + + $display("1 D with no change in data"); + DATA = 1; rd =1;rd_ack =0; + wait_clks(1); + $display("D"); + + DATA = 1; rd_ack =1; + wait_clks(1); + $display("2 D with no change in data"); + + + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/ivl_uvm_ovl_win_change_pass.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/ivl_uvm_ovl_win_change_pass.sv new file mode 100644 index 0000000..4d8a783 --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_change/ivl_uvm_ovl_win_change_pass.sv @@ -0,0 +1,85 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, rd,rd_ack,DATA; + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + // Instantiate OVL example - ovl_even_parity + ovl_win_change u_ovl_win_change ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .start_event(rd), + .test_expr (DATA), + .end_event(rd_ack) + + ); + + + + +initial begin + reset = 0; rd = 0; rd_ack = 0; + wait_clks(5); + + reset =1; + wait_clks(5); + + + + $display("Start testing"); + + $display("1 A with change in data"); + + DATA = 1; rd =1; rd_ack =0; + wait_clks(1); + $display("A"); + + + DATA = 0; rd_ack =1; + wait_clks(1); + $display("2 A with change in data"); + + + $display("1 B with change in data"); + DATA = 1; rd =1;rd_ack =0; + wait_clks(1); + $display("B"); + + DATA = 0; rd_ack =1; + wait_clks(1); + $display("2 B with change in data"); + + $display("1 D with change in data"); + DATA = 1; rd =1;rd_ack =0; + wait_clks(1); + $display("D"); + + DATA = 0; rd_ack =1; + wait_clks(1); + $display("2 D with change in data"); + + + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/Makefile b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/Makefile new file mode 100644 index 0000000..e253a9c --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/Makefile @@ -0,0 +1,18 @@ +all: clean ovl_win_unchange_pass ovl_win_unchange_fail help + +ovl_win_unchange_pass: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_win_unchange_pass.sv>& pass_comp.log + vvp a.out >& pass_run.log + +ovl_win_unchange_fail: + iverilog -g2012 -s test -I${IVL_UVM_HOME}/ivl_uvm_std_ovl/ -f flist ivl_uvm_ovl_win_unchange_fail.sv>& fail_comp.log + vvp a.out >& fail_run.log + +clean: + rm -fr a.out *.log *.vcd tee + +help: + @echo "(Targets - clean pass fail ovl_fifo_index_pass ovl_fifo_index_fail ovl_even_parity_pass ovl_even_parity_fail ovl_win_unchange_pass ovl_win_unchange_fail )" + + + diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/flist b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/flist new file mode 100644 index 0000000..17f991f --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/flist @@ -0,0 +1,3 @@ +${IVL_UVM_HOME}/ivl_uvm_std_ovl/ivl_uvm_ovl_inc.v +../ivl_uvm_ovl_clk_gen.sv +#../ivl_uvm_ovl_fifo_dut.sv diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_fail.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_fail.sv new file mode 100644 index 0000000..584fcee --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_fail.sv @@ -0,0 +1,115 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, rd,rd_ack; + reg [3:0]DATA; + + + // Instantiate OVL example - ovl_even_parity + ovl_win_unchange #( .width(4)) u_ovl_win_unchange ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .start_event(rd), + .test_expr (DATA), + .end_event(rd_ack) + + ); + + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + +initial begin + reset = 0; rd = 0; rd_ack = 0; + wait_clks(5); + + reset = 1; + wait_clks(5); + + $display("Start testing"); + + DATA = 0; rd =0; rd_ack =0; + wait_clks(5); + +// A + $display("1 A with change in data"); + + DATA = 4'b1111; rd =1; rd_ack =0; + wait_clks(5); + $display("A"); + + + DATA = 4'b1110; + wait_clks(5); + + rd_ack =1; + wait_clks(5); + + $display("2 A with data changing "); + +// B + + rd = 0; rd_ack =0; + wait_clks(5); + + $display("1 B with NOT change in data"); + + DATA = 4'b1100; rd =1; rd_ack =0; + wait_clks(5); + $display("B"); + + + DATA = 4'b1100; + wait_clks(5); + + rd_ack =1; + wait_clks(5); + + $display("2 B with NOT Data changing "); + +// C + + DATA = 0; rd =0; rd_ack =0; + wait_clks(5); + + $display("1 C with change in data"); + + DATA = 4'b0011; rd =1; rd_ack =0; + wait_clks(5); + $display("C"); + + + DATA = 4'b1110; + wait_clks(5); + + rd_ack =1; + wait_clks(5); + + $display("2 C with data changing "); + + + rd = 0; rd_ack =0; + wait_clks(5); + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule diff --git a/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_pass.sv b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_pass.sv new file mode 100644 index 0000000..1ae031a --- /dev/null +++ b/ivl_uvm_tests/ivl_uvm_ovl_tests/ivl_uvm_ovl_win_unchange/ivl_uvm_ovl_win_unchange_pass.sv @@ -0,0 +1,100 @@ +// This is linear queue / FIFO +// The queue length 1 + +`timescale 1ns/1ns + +// TB +module test; + + logic clk, reset, rd,rd_ack; + reg [3:0]DATA; + + + // Instantiate OVL example - ovl_even_parity + ovl_win_unchange #( .width(4)) u_ovl_win_unchange ( + .clock (clk), + .reset (reset), + .enable (1'b1), + .start_event(rd), + .test_expr (DATA), + .end_event(rd_ack) + + ); + + + //enabling the wave dump + initial begin + $dumpfile("dump.vcd"); + $dumpvars(0, test); + + end + + +initial begin + reset = 0; rd = 0; rd_ack = 0; + wait_clks(5); + + reset = 1; + wait_clks(5); + + $display("Start testing"); + + DATA = 0; rd =0; rd_ack =0; + wait_clks(5); + + +// B + + rd = 0; rd_ack =0; + wait_clks(5); + + $display("1 B with NOT change in data"); + + DATA = 4'b1100; rd =1; rd_ack =0; + wait_clks(5); + $display("B"); + + + DATA = 4'b1100; + wait_clks(5); + + rd_ack =1; + wait_clks(5); + + $display("2 B with NOT Data changing "); + +// C + + DATA = 0; rd =0; rd_ack =0; + wait_clks(5); + + $display("1 C with NOT change in data"); + + DATA = 4'b0011; rd =1; rd_ack =0; + wait_clks(5); + $display("C"); + + + DATA = 4'b0011; + wait_clks(5); + + rd_ack =1; + wait_clks(5); + + $display("2 C with NOT data changing "); + + + rd = 0; rd_ack =0; + wait_clks(5); + + $finish; + +end + + task wait_clks(input int num_clks = 1); + repeat (num_clks) @(posedge clk); + endtask : wait_clks + + ivl_uvm_ovl_clk_gen #(.FREQ_IN_MHZ(100)) u_clk_100 (clk); + +endmodule