Created by: Angelo Jacobo
Date: August 12,2021
- sdram_controller.v -> Controller for Synchronous Dynamic RAM. Specs are given below.
- comprehensive_tb.v -> Tests the sdram controller by writing to all 2^24 addresses of SDRAM then
reading it all back.
- key[0] writes deterministic data to all 2^24 addresses
- key[1] reads data from all addresses and checks if the data follows the
predetermined pattern
- key[2] injects 10240 errors when pressed along with key[0]
- number of errors read will be displayed on the seven-segment LEDs - bin2bcd.v -> binary to bcd converter to display the value of error_q to seven-segment LEDs
- LED_mux.v -> LED multiplexing module for seven-segment LEDs
- comprehensive_tb.ucf -> Constraint file for comprehensive_tb.v
This project implemented a controller for the SDRAM mounted on AX309 FPGA development board (i.e. Winbond W9825G6KH SDRAM) Specs of the controller are:
- Memory bandwidth is 316MB/s (can be checked by looking at the value of index_q register on Chipscope)
- Burst mode is "Full page" (i.e. burst of 512 words every read and write)
- Clock input must be 165MHz
- Auto-precharged is disabled (illegal for 165MHz clk)
- Clock latency of 3 (CL=2 is illegal for 165MHz clk)
- All banks are closed every refresh (in short no interleaving)
- Parameters can be configured on sdram_controller.v to suit any kind/brand of sdram device
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